Boolean Circuit Rewiring: Bridging Logical and Physical Designs.pdf

Boolean Circuit Rewiring: Bridging Logical and Physical Designs.pdf
 

书籍描述

内容简介

Demonstrates techniques which will allow rewiring rates of over 95%, enabling adoption of deep sub-micron chips for industrial applications

Logic synthesis is an essential part of the modern digital IC design process in semi-conductor industry. This book discusses a logic synthesis technique called “rewiring” and its latest technical advancement in term of rewirability. Rewiring technique has surfaced in academic research since 1993 and there is currently no book available on the market which systematically and comprehensively discusses this rewiring technology. The authors cover logic transformation techniques with concentration on rewiring. For many decades, the effect of wiring on logic structures has been ignored due to an ideal view of wires and their negligible role in the circuit performance. However in today’s semiconductor technology wiring is the major player in circuit performance degeneration and logic synthesis engines can be improved to deal with this through wire-based transformations. This book introduces the automatic test pattern generation (ATPG)-based rewiring techniques, which are recently active in the realm of logic synthesis/verification of VLSI/SOC designs.

  • Unique comprehensive coverage of semiconductor rewiring techniques written by leading researchers in the field
  • Provides complete coverage of rewiring from an introductory to intermediate level
  • Rewiring is explained as a flexible technique for Boolean logic synthesis, introducing the concept of Boolean circuit transformation and testing, with examples
  • Readers can directly apply the described techniques to real-world VLSI design issues
  • Focuses on the automatic test pattern generation (ATPG) based rewiring methods although some non-ATPG based rewiring methods such as graph based alternative wiring (GBAW), and “set of pairs of functions to be distinguished” (SPFD) based rewiring are also discussed

A valuable resource for researchers and postgraduate students in VLSI and SoC design, as well as digital design engineers, EDA software developers, and design automation experts that specialize in the synthesis and optimization of logical circuits.

目录

List of Figures x

List of Tables xiv

Preface xvii

Introduction xix

Resources xix

Intended Audience xix

Type conventions xix

Acknowledgements xx

1 Preliminaries 1

1.1 Boolean circuits 1

1.2 Redundancy and Stuck-at-faults 6

1.3 Automatic Test Pattern Generation (ATPG) 8

1.4 Dominators 9

1.5 Mandatory Assignments And Recursive Learning 10

1.6 Graph Theory And Boolean Circuits 12

1.7 References 14

2 Concept of Logic Rewiring 17

2.1 What is rewiring? 17

2.2 ATPG-based Rewiring Techniques 19

2.2.1 Add-First 19

2.2.2 Delete-First 27

2.3 Non-ATPG-based Rewiring Techniques 36

2.3.1 GBAW 36

2.3.2 SPFD 39

2.4 Why Are Rewiring Techniques Important? 45

2.5 References 48

3 Add-first And Non-ATPG-based Rewiring Techniques 53

3.1 Redundancy Addition and Removal (RAR) 54

3.1.1 RAMBO 54

3.1.2 REWIRE 55

3.1.3 RAMFIRE 58

3.1.4 Comparison Between RAR-based Rewiring Techniques 61

3.2 Node-based Network Addition and Removal (NAR) 62

3.2.1 Node merging 62

3.2.2 Node addition and removal 69

3.3 Other Rewiring Techniques 71

3.3.1 SPFD-Based Rewiring 71

3.4 References 90

4 Delete-first Rewiring Techniques 93

4.1 IRRA 95

4.1.1 Destination of Alternative Wires 99

4.1.2 Source of Alternative Wires 101

4.2 ECR 107

4.2.1 Destination of Alternative Wires 112

4.2.2 Source of Alternative Wires 119

4.2.3 Overview of The Approach of Error-Cancellation-based Rewiring 120

4.2.4 Complexity Analysis of ECR 121

4.2.5 Comparison Between ECR And Other Resynthesis Techniques 124

4.2.6 Experimental Result 128

4.3 FECR 134

4.3.1 Error Flow Graph Construction 137

4.3.2 Destination Node Identification 138

4.3.3 Source Node Identification 142

4.3.4 ECR is a special case of FECR 144

4.3.5 Complexity Analysis of FECR 144

4.3.6 Experimental Result 146

4.4 CECR 148

4.4.1 Preliminaries 148

4.4.2 Error Frontier 151

4.4.3 Cut-based Error Cancellation Rewiring 159

4.4.4 Verification of Alternative Wires 167

4.4.5 Complexity Analysis of CECR 168

4.4.6 Relationship Among ECR And FECR And CECR 168

4.4.7 Extending CECR for n-to-m Rewiring 169

4.4.8 Speed-up for CECR 169

4.4.9 Experimental Results 173

4.5 References 178

5 Applications 183

5.1 Area Reduction 183

5.1.1 Preliminaries 185

5.1.2 Our Methodology ("Long tail" vs. "Bump tail" curves) 187

5.1.3 Details of Our Approach 194

5.1.4 Experimental Results 197

5.2 Post-Placement Optimization 199

5.2.1 Wire Length Driven Rewiring-Based Post-Placement Optimization 200

5.2.2 Timing Driven Rewiring-Based Post-Placement Optimization 209

5.3 ECO Timing Optimization 220

5.3.1 Preliminaries 220

5.3.2 Nego-Rout Operation 222

5.3.3 Path Re-Structuring Operation 226

5.3.4 Experimental Results 227

5.4 Area Reduction in FPGA Technology Mapping 230

5.4.1 Incremental Logic Resynthesis (ILR): Depthoriented Mode 233

5.4.2 Incremental Logic Resynthesis (ILR): Areaoriented Mode 235

5.4.3 Experimental Results 237

5.4.4 Conclusion 252

5.5 FPGA Post-Layout Routing Optimization 254

5.5.1 Optimization by Alternative Functions 256

5.5.2 Optimization with Mapping-to-Routing Logic Rewirings 258

5.5.3 Optimization by SPFD-based Rewiring 273

5.6 Logic Synthesis for Low Power Using Clock Gating And Rewiring 274

5.6.1 Mechanism of Clock Gating 275

5.6.2 Rewiring-based optimization 279

5.7 References 285

6 Summary 291

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